Warning: fopen(/home/virtual/kwjs/journal/upload/ip_log/ip_log_2024-05.txt): failed to open stream: Permission denied in /home/virtual/lib/view_data.php on line 100 Warning: fwrite() expects parameter 1 to be resource, boolean given in /home/virtual/lib/view_data.php on line 101 Recent Progress of TGV Technology for High Performance Semiconductor Packaging

Recent Progress of TGV Technology for High Performance Semiconductor Packaging

Article information

J Weld Join. 2024;42(2):155-164
Publication date (electronic) : 2024 April 30
doi : https://doi.org/10.5781/JWJ.2024.42.2.2
* Dept. of Materials Science and Engineering, University of Seoul, Seoul, 02504, Korea
†Corresponding author: jpjung@uos.ac.kr
Received 2024 March 7; Revised 2024 March 14; Accepted 2024 March 27.


In recent semiconductor packaging, the adoption of through silicon via (TSV) technology has become crucial for the integration of 2.5 and 3D Si chips, and interposers. The TSV offers significant advantages including high interconnect density, shortened signal pathways, and improved electrical performance. However, challenges such as electrical loss, substrate warpage, and high manufacturing costs are associated with TSV implementation. In contrast, glass-based through-glass vias (TGVs) exhibit promising characteristics such as excellent insulation properties, cost-effectiveness, and variable coefficient of thermal expansion (CTE) values that mitigate warpage in stacked devices. Moreover, they facilitate miniaturization and support high-frequency applications. This paper provides an overview of recent advancements in glass substrate, TGV drilling techniques, functional layer depositions, and Cu-filling processes in semiconductor packaging evolution.

1. Introduction

With the development of mobile devices and Internet of Things (IoT), research on three-dimensional (3D) packaging technology is being conducted to achieve smaller and thinner package sizes and higher electrical reliability. Although semiconductor traditionally uses silicon substrates, the demand for glass substrates is also increasing to meet the requirements of advanced electronic components such as mobile electronic devices and IoT. The market for Through Glass Via (TGV) substrates was estimated at USD 60 million in 2022, and is expected to reach USD 480.5 million by 2029, with a compound annual growth rate of 34.2% during the forecast period from 2023 to 20291). Glass is considered a suitable material for RF communication and interposer applications due to its low dielectric constant, low electrical loss, and variable coefficient of thermal expansion (CTE), necessitating the formation of precise TGVs for electrical connections between chips2). Fig. 1 shows an example of a 2.5D semiconductor packaging application with glass and TGV as an interposer.

Fig. 1

Glass interposer adopted to a 2.5D semiconductor package

TGV allows for denser interconnections compared to traditional wire bonding, enabling the placement of more electrical signals in a limited space. TGVs implemented in glass substrates help suppress issues like crosstalk and insertion loss, which are common with silicon-based TSVs3). Glass’s excellent RF transparency allows high-frequency signals to be easily transmitted through TGVs, resulting in low electrical loss at high frequencies and high performance in wireless communication and radar applications. Furthermore, the stiffness and insulation of glass substrates, their low cost, and the benefits of ultra-thin flexible glass substrates about 100 ㎛ thick offer advantages in the electronic packaging field4). Moreover, the thermal and mechanical stability of glass substrates allows for denser interconnections and scalability, enhancing semiconductor performance.

Optimizing the CTE is essential to achieve reliable 3D packaging. Unlike silicon, amorphous glass has a variable CTE, which minimizes warpage caused by CTE mismatches with other materials5). Fig. 2 shows the warpage caused by CTE mismatches in 2.5D packaging: (a) shows the warpage with a silicon interposer, while (b) demonstrates how adjusting the CTE can minimize warpage between the glass and the substrate.

Fig. 2

2.5D packaging using different interposer material, (a) Si interposer, (b) Glass interposer

Warpage is also a critical issue in advanced packaging areas such as FOWLP (Fan-Out Wafer Level Package), which features high integration and excellent heat dissipation characteristics. The thinner thickness of FOWLP compared to traditional packages, and the fact that it is processed at the wafer level, results in much greater warpage than at the die level6). The adjustable CTE of glass materials minimizes problems caused by the substrates becoming thinner and larger, showing high applicability in advanced 3D packaging fields. On the other hand, challenges such as lower thermal conductivity compared to Si and cracks due to surface defects need to be addressed. Recently, as Intel announced at Semicon Japan regarding the “next evolution in advanced semiconductor packaging substrate technologies” with TGV and related technologies, significant progress has been made in various associated technological fields7).

This study investigates high-performance and reliable TGV formation technologies and related research for semiconductor 3D packaging on glass substrates.

2. TGV Formation Technologies

2.1 Laser-Induced Selective Etching (LISE)

LISE is a TGV formation technology that uses lasers to locally etch the irradiated area to form patterns. Using lasers with very short pulse widths ranging from femtoseconds to picoseconds allows for the concentrated irradiation of high-energy laser pulses in a very short duration. In the process of forming TGVs on glass substrates, the laser delivers high energy locally to the surface of the glass in a short time8). This causes thermal- mechanical effects that change the surface expansion and density of the glass, thereby creating areas sensitive to chemical etching. Chemical etching with solutions such as KOH in these areas forms nano-diffraction grating structures known as nanocraters, altering the surface of the glass. By adjusting the pulse energy of the laser irradiation and the chemical etching conditions, the size of the nanocraters can be controlled, and the desired via shapes can be obtained9).

Nano-diffraction grating structures have also been reported in fused silica substrates using LISE. Jia et al.10) used a single pulse femtosecond laser with a wavelength of 1,030 nm to irradiate parallel line patterns at different pulse intervals, followed by selective etching with KOH solution at 85°C for 5 hours. The pulse duration is 290 fs, and the pulse repetition frequency is 1 MHz. SEM measurements showed that at pulse intervals of 1 μs and 2 μs, selective etching did not occur due to thermal accumulation and diffusion, resulting in dispersed nanostructures. From a pulse interval of 3 μs, thermal energy diffused to the surroundings, resulting in the observation of regular and connected nano-diffraction grating structures. However, beyond a pulse interval of 5,000 μs, although nano diffraction gratings appeared, they were not interconnected, preventing etching from proceeding. In conclusion, the creation and connection of nano diffraction grating structures are reported as the main mechanisms in pattern formation during the selective etching process with femtosecond lasers.

Kim et al.11) studied the effects of the duration and pulse waveform of the ultrashort pulse laser on the TGV formation rate in borosilicate glass. In the experiments, single pulses and dual pulses with intervals of 213 ps, 10 ns, and 500 ms were used. After irradiating each pulse for 0.2 to 1 ps and then using KOH solution, the formed TGVs were compared through cross-sections using OM and SEM. The comparison showed that as the pulse duration increased from 0.2 ps to 1 ps, the diameter of the TGV decreased and the depth increased, but only the dual pulse with a 10 ns interval showed a consistent depth. This is because different carrier-related phenomena occur dominantly depending on the time interval between pulses. In the dual pulse with a 213 ps interval, additional photons irradiate while activated carriers are in the excited state due to the electrons receiving energy, increasing the electrons’ kinetic energy and thus the penetration depth of the photons. However, for the pulse with a 10 ns interval, electrons return to the ground state and additional photons irradiate, resulting in dominant thermal diffusion. In this case, the length of thermal diffusion does not vary significantly with the pulse duration, so the depth of the TGV remained consistent.

For a pulse duration of 1 ps, the depth of the TGV hole was the deepest at 22.39 ㎛ for the dual pulse with a 213 ps interval, and a nano diffraction grating with a thickness of 156±22 nm was observed. In conclusion, dual pulses with a ps interval can enhance the formation rate of TGV by strengthening the electrons’ kinetic energy, proving that increasing the electrons’ kinetic energy is more advantageous for machining than thermal diffusion.

The concentration of the etching solution is also a major factor affecting the TGV profile. Chen et al.12) reported that adjusting the concentration of the HF etching solution in borosilicate glass can improve the taper of the TGV sidewalls. The laser used in the experiments was a picosecond single pulse laser, with a pulse energy of 55 μJ and a pulse width of 16 ps. Three identical samples irradiated by a single pulse laser beam were etched with HF solutions of 10%, 5%, and 3% concentrations, respectively, and the angle of the TGV sidewalls was measured through cross-sections. For TGV with a surface diameter of 60 ㎛, as the concentration of the HF solution decreased from 10% to 3%, the angle of the via sidewalls increased from 80.65° to 84.18°, effectively improving the TGV profile. Meanwhile, as the number of pulses increased from 1 to 10, the angle of the via sidewalls increased from 80.65° to 81.13°, but the increase was minimal. Fig. 3 is a schematic representation of the LISE technology used in the experiments and the cross-section of the formed TGV.

Fig. 3

(a) Schematic drawing of LISE process, (b) Cross section view of TGV structure on borosilicate glass

2.2 Electrical Discharging Method (EDM)

EDM is a TGV formation technology that uses electrical discharge, utilizing high voltage and current to form precise structures on glass substrates. This technique involves maintaining the glass between two aligned electrodes in two steps. First, the electrical discharge is concentrated and generates heat, which locally reduces the viscosity of the glass. Second, the glass is extracted through joule heating, creating a hole. The EDM process allows for the formation of holes with high aspect ratios in a relatively short time compared to traditional TGV formation methods13). EDM uses electrical discharge alone, but methods like ECDM (electrical chemical discharging method), which combine electrical discharge with a chemical reaction by adding electrolytes, are also used.

Harindra et al.14) formed TGVs on fused silica substrates using the ECDM process with KOH electrolyte and fabricated 3D inductors. Inductors on silicon substrates require a process to deposit an insulating layer due to their low resistivity. On the other hand, inductors fabricated on glass substrates do not require an insulating layer, simplifying the process, and the transparent optical characteristics of glass make it easier to detect defects during production. The experiment was conducted on a 2-inch diameter, 520-㎛ thick fused silica substrate, using stainless steel multi-tips in 2x5 and 2x2 arrays to form holes. The average top and bottom diameters of TGVs formed by the 140±10 ㎛ size multi-tips were measured at 580±71 ㎛ and 286±45 ㎛, respectively. Spiral and toroidal inductors were fabricated, and the measured resistance of the inductors was 338 m Ω and 168 mΩ, respectively. This research confirmed the applicability of the TGV process for the fabrication of 3D inductors. Fig. 4 is a schematic representation of the process for fabricating 3D inductors on a fused silica substrate.

Fig. 4

Schematic drawing for the fabrication of the 3D inductors on fused silica substrate, (a) Fused silica substrate, (b) TGV fabricated by ECDM, (c) Substrate bonded to carrier substrate, (d) Copper electroplating, (e) Copper seed layer polished away, (f) Ti/Cu layer deposition on both sides, (g) Lithography on both sides to define RDL mold, (h) Cu electroplating, resist removal and seed layer wet etching

Research has been conducted to improve the characteristics of TGVs formed by EDM and ECDM, using additives or laser machining.

Zhixiang et al.15) conducted research to enhance the uniformity and repeatability of TGVs formed by ECDM by adding polyacrylamide (PAM), a nontransferring function (NTF) electrolyte, to the KOH electrolyte. NTF electrolytes, which do not have high electrical transmission characteristics, are used to control electrical effects during the ECDM process. Unlike the conventional KOH electrolyte, using an NTF electrolyte can achieve damping and confinement effects. The damping effect refers to reducing vibrations generated during the ECDM process. During ECDM machining, micro-vibrations occur on the glass surface due to discharges between the electrolyte and the electrode, negatively affecting precision machining. The confinement effect refers to limiting the area where discharge occurs during ECDM machining, enabling precision machining. By inducing the discharge to focus on a specific area through the confinement effect, precise TGVs can be formed. In the experiment, NTF electrolyte concentrations ranging from 0.1 wt% to 0.9 wt% were added to the KOH electrolyte, and ECDM machining was conducted on soda-lime glass substrates. The results showed that an array of 81 micro-holes fabricated with 0.5 wt% NTF electrolyte had a standard deviation of overcut of 3.34 ㎛, a significant improvement compared to the standard deviation of 9.79 ㎛ with KOH electrolyte alone. The width of the heat-affected zone (HAZ) generated during the TGV formation process also decreased by 64.81%, proving the usefulness of NTF electrolytes in the ECDM process.

Harmesh et al.16) conducted research to enhance the performance of EDM using electrodes augmented with carbon nanotubes (CNT). In the experiment, nano-powder form CNTs were used on steel substrates composed primarily of carbon and chromium, and the CNT particles were mixed with the dielectric during the EDM process, generating sparks and contributing to an improved erosion rate of the workpiece. Sparks were uniformly distributed among CNT particles, improving the workpiece’s material removal rate (MRR) and surface roughness (SR). The results showed that the EDM process with 4 g of added CNTs had an MRR 80% higher and an SR 67% lower compared to traditional EDM. In conclusion, the concentration of added CNTs is a crucial parameter that significantly affects MRR and SR in the EDM process.

Zhao et al.17) conducted research on laser-assisted (LA) ECDM, which combines laser machining and ECDM. In the experiment, a Nd:YVO4 laser with a wavelength of 1064 nm and a pulse duration of 12 ps was used, and ECDM was conducted in NaOH electrolyte after laser irradiation. The results showed that machining accuracy improved in the ECDM process conducted after laser irradiation due to the confinement effect. Additionally, holes machined only with the laser had a V-shape with a large taper. In LA-ECDM, the profile of the hole transformed from a V-shape to a U-shape, significantly improving the taper.

The formation of TGV by electrochemical discharge machining has the advantage of manufacturing a large number of TGVs in a short time, but the electrode wear caused by the heat generated during machining negatively affects the TGV profile. Electrode wear directly impacts the accuracy of machining and the reliability of formed TGVs, and since about 70% of EDM machining costs are attributed to electrode replacement, reducing wear is crucial18).

Jafferson et al.19) conducted experiments to reduce electrode wear through cryogenic cooling. In the experiments, liquid nitrogen at -185°C was used as the cryogenic cooling material, with copper and tungsten as electrode materials and 1 mm thick stainless steel as the substrate. The results showed that the tool wear rate (TWR) decreased by 58% for tungsten electrodes and 35% for copper electrodes, demonstrating that cryogenic cooling significantly reduces tool wear. Additionally, Vickers hardness tests on cryogenically treated electrodes showed an increase in hardness of 120% for tungsten electrodes and 17% for copper electrodes, proving the effectiveness of cryogenic cooling.

3. Functional Thin Film Formation and Cu Filling in TGV

3.1 Coating of Functional Thin Films on TGV Inner Walls

Functional thin films are thinly deposited or coated films designed to provide specific physical, chemical, or electrical properties. These films offer various functions and are used across numerous technological fields. Each functional film is designed according to the requirements of its application area and plays a crucial role in the TGV manufacturing process.

Uses of thin films include (1) Seed layer: Used as a coating for smooth electroplating of filling metals like Cu and Au, (2) Insulating layer: Used to electrically isolate the TGV and prevent current leakage and interference between adjacent TGVs, and (3) Adhesion layer: Used to strengthen the bond between the seed layer and insulating layer20,21).

For forming thin films on glass substrates, dry methods including sputtering were common, but there are challenges in achieving uniform film thickness in high aspect ratio TGVs. In contrast, wet methods, which involve immersing the glass substrate in a solution for film formation, allow for uniform and consistent formation on TGV and glass surfaces. If the seed layer is not properly formed on the TGV inner walls, defects such as incomplete Cu filling can occur later22).

Chen et al.23) formed a metal seed layer in TGV using Ni activation and electroless Ni-P plating. The experiments used photoreactive glass composed of Li-Al-Si; the chemical reactions in Ni-P plating are as follows( Eq. 1,2).


Ni-P coated specimens were annealed in the atmosphere at 200-450°C for 30 minutes, with a temperature rise rate of 120°C/h below 150°C and 60°C/h above. The results showed that after annealing above 350°C, the adhesion of the plating layer significantly improved, and oxidation films formed above 400°C, increasing electrical resistance. According to other research reports24-27), the Ni-P seed layer crystallizes after heat treatment, showing Ni and Ni3P phases. The Ni-P phase is primarily amorphous, and dendritic crystallization, similar to tree branches, occurs after annealing, improving adhesion to TGV. Consequently, the nickel seed layer effectively coated vias with a 10:1 aspect ratio, and the average layer thickness was about 200 nm, showing uniform plating characteristics inside the via.

Inoue et al.28) formed a Cu seed layer on a glass substrate using wet plating, specifically, electroless plating of a Cu thin film followed by electroplating. The results showed that on a Na glass substrate, the adhesion strength of Cu was 0.6 kN/m, and on a non-alkali glass substrate, it was about 0.4 kN/m.

Takayama et al.29) proposed a method to form a Cu seed layer inside TGV in non-alkali glass substrates by combining low-vacuum high-speed sputtering and electroplating. During high-speed sputtering, with a film pressure of 0.5-5 Pa, power of 35 kW, and sputtering time of 28 seconds, a 3 ㎛ Cu film was formed on the flat part of the TGV substrate, and a 0.29 ㎛ Cu film was formed in the center of the TGV with an aspect ratio of 3.75 (via diameter 80 ㎛, depth 300 ㎛). After sputtering, sulfuric and pyrophosphoric acid plating baths were used for electroplating, with the pyrophosphoric acid showing adhesion strength of Cu exceeding 1.0 kN/m.

Yiu et al.30) achieved high aspect ratio TGV filling on a fused silica substrate by applying an adhesion promoting layer (APL) of solution-based metal oxide. APL was deposited on the sidewalls of TGV by spin coating, followed by electroless plating of a Cu layer and electroplating using DC current. The results showed the formation of HAR-TGVs without voids, with a length of 345 ㎛ and a diameter of 25 ㎛. The APL layer can be deposited by various methods such as dip coating and spin coating, and achieving HAR-TGVs under DC waveforms rather than complex PPR waveforms highlights its significance.

Meanwhile, Shigeo et al.31) proposed a wet plating process that allows for the direct formation of Cu films on glass without an adhesion layer between the Cu and glass. Initially, the non-alkali glass substrate was ultrasonically cleaned, alkali-degreased, and UV-irradiated to remove organic materials from the glass surface and enhance adhesion. A 3 ㎛ Cu layer was plated as a seed layer through the wet plating process, followed by electroplating and SAP (semi-additive process) to coat 15 ㎛ thick copper on the sides, front, and back of TGV. The results showed that both the wet-plated Cu seed layer and the electroplated copper were uniformly plated, achieving high adhesion strength of 0.35 kN/m and excellent surface flatness of the glass. The measured resistance of the TGV was below an average of 6.71 mΩ /via. Wet plating for TGV coating can be applied to large glass substrates and allows the process to proceed without additional functional thin film coatings, offering the advantages of being inexpensive and efficient.

Hariki et al.22) also proposed a film attachment and closure plating method to fill Cu in TGV without forming a seed layer inside and reported successful Cu filling inside the via.

3.2 Cu Plating for Filling TGV and TSV

Cu filling of TGV and TSV mainly uses electroplating. Electroplating is a method that coats a specific surface with a target metal by moving metal ions to the cathode through a current. During the Cu electroplating process, current flows through a plating solution containing Cu ions, and the Cu ions move to the cathode, where they receive electrons and are reduced to copper. The reduced Cu ions are deposited on the surface of TSV and TGV, forming a plating layer.

The metal layer formed inside TGV and TSV by electroplating is influenced by the applied current density and waveform. In DC (direct current) Cu filling, higher current densities at the via opening lead to thicker plating at the top than the bottom, connecting the via opening with Cu first, making it prone to defects such as voids and seams inside the via. Such defects can be improved by applying pulse current, optimizing plating solutions with additives, and using ultrasound32,33).

Additives used for plating solution optimization include inhibitors, accelerators, and levelers. Inhibitors and accelerators control the speed of metal deposition during electroplating, while levelers induce uniform metal deposition, improving the quality of electroplating.

Regarding additives, Ling et al.34) conducted research on the synergistic effects of inhibitors and accelerators for Cu filling in TGV. In the experiment, tapered vias with a depth of 150 ㎛ were used, with the diameter at the top being 50 ㎛ and at the bottom 20 ㎛. The plating solution used was 99.7 g/L CuSO4, 10 g/L H2SO4, and 50 ppm Cl-, with novel inhibitor A, accelerator B, and leveler C, and deposition was carried out at current densities of 0.5 ASD (amps per square decimeter), 1 ASD, and 1.5 ASD. In the first experiment, with the ratio of inhibitor, accelerator, and leveler at 50:1:1.25, the via was perfectly filled without voids in 2.25 hours at 1 ASD. At lower concentrations of the inhibitor, the synergistic effect of the inhibitor and accelerator contributed to an increase in the surface thickness of the via, increasing the difference in surface thickness between the top and bottom of the via. However, as the concentration of the inhibitor increased, inhibitor A molecules preferentially adsorbed on the surface of the via, slowing down the deposition rate. As a result, the thickness of the via surface decreased, and the surface plating at the top and bottom was consistently maintained. Consequently, at an inhibitor, accelerator, and leveler ratio of 60:1:1, the via was perfectly filled without voids in 1.5 hours at a higher current density of 1.5 ASD.

Jin et al.35) researched the effect of the molecular weight of PVP (polyvinylpyrrolidone) used as a leveler in Cu filling of TGV on the formation of an inhibition layer on the Cu surface. The experiment used an aqueous electrolyte containing 0.94 M CuSO4, 0.31 M H2SO4, 2 mM HCl, with inhibitor PEG (polyethylene glycol), accelerator bis(3-sulfopropyl) disulfide (SPS), and leveler PVP of molecular weights 10,000, 29,000, 360,000, and 1,300,000 g/mol. The TGVs used in the experiment had a height of 400 ㎛ and a tapered structure with an opening diameter of 80 ㎛ and a midpoint diameter of 40 ㎛. The results showed that smaller molecular weight PVP (10,000 g/mol) formed a denser inhibition layer on the Cu surface, effectively inhibiting Cu electrode plating and inducing defect-free filling. Conversely, the larger molecular weight PVP (360,000 g/mol) layer was less dense and contained many defects that could accommodate accelerators. This suggests that steric hindrance between adsorbed PVP molecules increases with molecular weight, hindering the formation of a dense inhibition layer on the Cu surface as the molecular weight increases. The research findings that the molecular weight of polymer additives affects the structure and competitive adsorption of the adsorbate highlight the importance of selecting the appropriate polymer additives to enhance the performance of the Cu filling process.

Optimizing the plating solution with additives shows excellent effects in preventing defects under a steady DC current waveform. However, due to the nature of DC current, completely preventing voids is challenging due to the current density differences at the via locations when high current is applied. To solve this problem, electroplating methods using PPR (periodic pulse reverse) waveforms are currently being used. PPR waveform consists of pulse current, reverse pulse current, and off-pulse periods, enabling superconformal filling of vias by repeating pulse and reverse pulse currents with off-pulses. During the pulse current period, Cu is plated inside the via, and during the reverse pulse period, the excessively plated Cu layer dissolves back. During the off-pulse, copper ions diffuse back into the plating solution, evening out ion concentration in the via and preventing preferential copper plating on the surface36).

Laser-machined TGVs generally have a tapered via structure, which can have a slope on one side or both sides depending on the laser drilling method. The researchers37,38) have investigated the degree of Cu filling in straight and tapered Si vias using PR and PPR currents. Under the same PR current conditions, the filling rate of straight vias was a maximum of 45% at a current density of 2.29 mA/cm², while tapered vias showed a maximum filling rate of 71% at a current density of 3.04 mA/cm², indicating higher rates for tapered vias compared to straight ones.

In the PPR current waveform, tapered vias showed a 100% Cu filling rate at an average current density of 5.85 mA/cm², overall indicating higher filling rates with PPR waveforms compared to PR. Fig. 5 is the representation of the Cu filling ratio of vertical and tapered vias according to current density in PR and PPR waveforms.

Fig. 5

Cu filling ratio of straight and tapered vias according to PR and PPR current density (electroplating time; 1hr)37,38)

Regarding electroplating with PPR waveforms, the researchers39) conducted a study on staged PPR using three levels of current density to improve processing time. In the initial stage, a low current density is applied for conformal plating on the entrance, walls, and bottom of the via. In the intermediate stage, a medium current density is applied for superconformal plating inside the via, and finally, a high current density is applied to completely fill the via with Cu. Consequently, the final stage compensates for the time spent at low current densities in the initial and middle stages, achieving defect-minimized Cu plating. These results demonstrate the importance of optimizing current waveforms for fast and reliable Cu filling.

In Cu filling of TSVs, void-free filling was achieved using PPR current waveforms without additives. In experiments by Zhu et al.40), applying a pulse current of 0.4 A/dm² and a reverse pulse current of -0.8 A/dm² to TSVs with a diameter of 50 ㎛ resulted in V-shaped copper layer growth and achieved void-free superconformal plating. Comparing results according to current waveforms, DC plating conducted at the same 0.4 A/dm² as the pulse current revealed large voids inside. The reverse pulse contributed to the dissolution of Cu, aiding in the V-shaped growth of the copper layer, and the off-pulse extended the diffusion time for copper ions, balancing ion concentration inside the via. However, in electroplating of Cu using PPR, an increase in current density led to the formation of an inverted V-shaped structure at the bottom of the via, resulting in voids. Fig. 6 is a schematic representation of Cu filling using PPR at (a) high and (b) low current densities. The direct V structure formed at the top of the via increased as the current density decreased, and at low current densities, the direct V structure dominated over the inverted V structure, achieving void-free filling.

Fig. 6

Schematic drawing of the Cu filling process using PPR current, (a) with high current density, (b) with low current density

Inoue et al.28) confirmed uniform Cu filling in TGVs on an 8” non-alkali glass wafer through electroless Cu thin film formation and Cu plating.

While previous studies used a bottom-up sectional electroplating approach where Cu accumulates from the bottom to the top, Ke et al.41) conducted research on a double-sided plating process. Double-sided plating is a method that simultaneously plates both sides of the target, applicable when plating is needed on both sides of the substrate. In the experiment, Ti was used as a diffusion barrier and Cu as a seed layer, achieving uniform and void-free TGV filling by adjusting parameters such as current density, additives, and plating solution. The double-sided electroplating process faces challenges, such as unequal flow rates of plating solution and differences between the two sides of the substrate, requiring adjustment of current and parameters at various stages of electroplating. However, it has advantages over sectional electroplating, such as faster filling time and applicability to substrates with different patterns on each side.

4. Conclusion

The field of high-density, high-performance semi-conductor packaging has made significant progress owing to the adoption of TSV technology to integrate 2.5D and 3D Si chips and interposers. While TSV offers advantages such as increased interconnect density and shortened signal paths, efforts are ongoing to overcome its drawbacks, including electrical loss, substrate warpage, and high manufacturing costs. As an alternative to address the disadvantages of TSV technology, glass-based TGVs offer advantages in insulation performance, cost-effectiveness, and applicability in highfrequency domains. Additionally, due to their variable CTE values, they effectively mitigate warpage in stacked devices such as 2.5D and 3D structures. As a result, it is garnering attention as a next-generation semiconductor packaging technology, with numerous studies underway. This technology is expected to improve performance, reliability, and cost efficiency in the semiconductor packaging field due to continuous advancements in glass substrates, TGV drilling technology, functional layer coating, and Cu filling processes.


This research was supported by the Ministry of Trade, Industry and Energy (MOTIE) and the Korea Institute for Advancement of Technology (KIAT). (P0018010, 2024)


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Fig. 1

Glass interposer adopted to a 2.5D semiconductor package

Fig. 2

2.5D packaging using different interposer material, (a) Si interposer, (b) Glass interposer

Fig. 3

(a) Schematic drawing of LISE process, (b) Cross section view of TGV structure on borosilicate glass

Fig. 4

Schematic drawing for the fabrication of the 3D inductors on fused silica substrate, (a) Fused silica substrate, (b) TGV fabricated by ECDM, (c) Substrate bonded to carrier substrate, (d) Copper electroplating, (e) Copper seed layer polished away, (f) Ti/Cu layer deposition on both sides, (g) Lithography on both sides to define RDL mold, (h) Cu electroplating, resist removal and seed layer wet etching

Fig. 5

Cu filling ratio of straight and tapered vias according to PR and PPR current density (electroplating time; 1hr)37,38)

Fig. 6

Schematic drawing of the Cu filling process using PPR current, (a) with high current density, (b) with low current density