| 3D 패키지용 관통 전극 형성에 관한 연구 |
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| Fabrication of Through-hole Interconnect in Si Wafer for 3D Package |
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Dae-Gon Kim, Jong-Woong Kim, Sang-Su Ha, Jae-Pil Jung, Young-Eui Shin, Jeong-Hoon Moon, Seung-Boo Jung |
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| Abstract |
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The 3-dimensional (3D) chip stacking technology is a leading technology to realize a high density and high performance system in package (SiP). There are several kinds of methods for chip stacking, but the stacking and interconnection through Cu filled through-hole via is considered to be one of the most advanced stacking technologies. Therefore, we studied the optimum process of through-hole via formation and Cu filling process for Si wafer stacking. Through-hole via was formed with DRIE (Deep Reactive Ion Etching) and Cu filling was realized with the electroplating method. The optimized conditions for the via formation were RF coil power of 200 W, etch/passivation cycle time of 6.5 : 6 s and SF6 : C4F8 gas flow rate of 260 : 100 sccm. The reverse pulsed current of 1.5 A/dm2 was the most favorable condition for the Cu electroplating in the via. The Cu filled Si wafer was chemically and mechanically polished CMP) for the following flip chip bumping technology. |
| Key Words:
Si chip stacking, 3D package, SiP, Through hole, Cu filling, Flip chip |
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